1. Field
This invention relates to data converters, and more specifically, to pipelined successive approximation analog-to-digital converters.
2. Background
The successive approximation register (SAR) analog-to-digital converters (ADCs) have been widely used as a power-efficient candidate for medium speed and medium to high resolution applications. To overcome the speed limit imposed by the technology, time-interleaving has often been employed for SAR ADCs. However, several problems have emerged with increasing the number of constituent time interleaved SAR ADC cores (sub-ADCs) and/or with the use of active elements in a pipelined SAR ADC. Known issues with direct time-interleaving include increased input loading, stringent sub-ADC matching and timing skew requirements, increased power and increased area. Furthermore, pipelining with active elements typically used to provide amplification leads to poor power efficiency and the necessity of complex error calibration with a changing environment.